Interconnection of small assembled microelectronic chips onto a substrate is made much more facile if those chips are planarized, thereby avoiding the need for interconnects to span a step edge. Planarization of chips has been extensively studied, and conventional approaches typically require pre-patterning of a recess into which the chip is placed, or the use of very thin chips and coating of resist over the chips followed by etching back or the opening of vias to make contact. A problem with these approaches is that they require substantial processing that greatly increases manufacturing costs and introduces complications that can lead to reduced production yields.
What is needed is a cost-effective and reliable process for generating micro-assemblies in which multiple micro-objects (e.g., microelectronic chips) are secured to a common substrate such that surfaces of all of the micro-objects are coplanar with the substrate surface.